Gate Engineering on the Analog Performance of DM-DG MOSFETs with High K Dielectrics

Considerable challenges are encountered when bulk CMOS devices are scaled into the sub-100 nm regime for higher integrated circuit (IC) density and performance. Due to their excellent scalability and better immunity to short channel effects, double-gate (DG) MOSFETs are being easily assessed for CMOS applications beyond the 70 nm of the SIA roadmap. For channel lengths below 100 nm, DG MOSFETs still show considerable threshold voltage roll off and to overcome this effect, different gate engineering techniques can be widely used. In this paper, we investigate the influence of gate engineering on the analog and RF performances of dual material double gate (DM-DG) MOSFETs for systemon-chip applications with high K dielectrics using a 2D device simulator. Equivalent oxide thickness (EOT) of gate oxide can be reduced by the usage of high K dielectric materials. The gate engineering technique used here is the dual metal gate technology. This novel structure shows better immunity to DIBL and improved analog performance like trans conductance generation factor, early voltage, output resistance.